View PE43705-14_8022324.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2013 peregrine semiconductor corp. all rights reserved. page 1 of 18 document no. doc-47814-2 | www.psemi.com product description the pe43705 is a 50 ? , harp? technology-enhanced, 7-bit rf digital step attenuator (dsa) designed for use in 3g/4g wireless infrastructure and other high performance rf applications. this dsa is a pin-compatible upgraded version of pe43703 with higher power handling and a wider frequency, control voltage and operating temperature range. an integrated digital control interface supports both serial and parallel programming of the attenuation, including the capability to program an initial attenuation state at power-up. covering a 31.75 db attenuation range in 0.25 db, 0.50 db, or 1 db steps, it maintains a monotonic step response from 50 mhz through 8 ghz. pe43705 also features safe attenuation state transitions and is offered in a 32-lead 5x5 mm qfn package. in addition, no external blocking capacitors are required if 0v dc is present on the rf ports. the pe43705 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate. peregrine?s harp? technology enhancements deliver high linearity and excellent harmonics performance. it is an innovative feature of the ultracmos ? process, offering the performance of gaas with the economy and integration of conventional cmos. pe43705 figure 1. functional diagram features ?? attenuation options: covers a 31.75 db range in 0.25 db, 0.5 db, or 1.0 db steps ?? 0.25 db monotonicity for 6 ghz ?? 0.50 db monotonicity for 7 ghz ?? 1.00 db monotonicity for 8 ghz ?? safe attenuation state transitions ?? high power handling ?? 31 dbm, pulsed @ 8 ghz ?? 28 dbm, cw @ 8 ghz ?? high linearity: +65 dbm iip3 ?? 1.8v control logic compatible ?? 105c operating temperature ?? programming modes ?? direct parallel ?? latched parallel ?? serial ?? serial addressable ?? high-attenuation state @ power-up (pup) ?? esd performance ?? 1.5kv hbm on all pins product specification ultracmos ? rf digital step attenuator, 7-bit, 31.75 db 50 mhz ? 8 ghz figure 2. package type 32-lead 5x5 mm qfn 71-0052
document no. doc-47814-2 | ultracmos ? rfic solutions page 2 of 18 ?2013 peregrine semiconductor corp. all rights reserved. pe43705 product specification table 1. electrical specifications: 0.25 db steps @ +25c, v dd = 2.3v to 5.5v, (z s = z l = 50 ? ) unless otherwise noted note 1: the input 0.1db compression point is a linearity figure of merit. refer to table 5 for the operating rf input power (50 ? ) parameter condition frequency min typ max unit operating frequency 50 6000 mhz attenuation range 0.25 db step 0 ? 31.75 db insertion loss 50 mhz ? 2.2 ghz 2.2 ghz ? 4 ghz 4 ghz ? 6 ghz 1.3 1.7 2.4 1.6 2.0 2.8 db db db attenuation error 0 db ? 15.75 db attenuation settings 50 mhz ? 2.2 ghz + (0.15 + 1.5% of attenuation setting) - (0.1 + 1% of attenuation setting) db db >2.2 ghz ? 4 ghz + (0.15 + 3% of attenuation setting) - (0.1 + 1% of attenuation setting) db db >4 ghz ? 6 ghz + (0.2 + 6% of attenuation setting) - (0.15 + 1% of attenuation setting) db db 16 db ? 31.75 db attenuation settings 50 mhz ? 2.2 ghz + (0.15 + 1.5% attenuation setting) - (0.1 + 1.5% of attenuation setting) db db >2.2 ghz ? 4 ghz + (0.15 + 4% attenuation setting) - (0.1 + 0.75% of attenuation setting) db db >4 ghz ? 6 ghz + (0.25 + 7.5% of attenuation setting) - (0.2 + 0% of attenuation setting) db db return loss input port 50 mhz ? 4 ghz 4 ghz ? 6 ghz 20 15 db db return loss output port 50 mhz ? 4 ghz 4 ghz ? 6 ghz 17 13 db db relative phase 0 db ? 31.75 db attenuation settings 50 mhz ? 6 ghz 55 deg input 0.1db compression point 1 50 mhz ? 6 ghz 34 dbm input ip3 two tones at +18 dbm, 20 mhz spacing 6 ghz 65 dbm rf trise/tfall 10% / 90% rf 568 ns switching time 50% ctrl to 90% or 10% rf 1 s
pe43705 product specification ?2013 peregrine semiconductor corp. all rights reserved. document no. doc-47804-2 | www.psemi.com page 3 of 18 table 2. electrical specifications: 0.5 db steps @ +25c, v dd = 2.3v to 5.5v, (z s = z l = 50 ? ) unless otherwise noted parameter condition frequency min typ max unit operating frequency 50 7000 mhz attenuation range 0.5 db step 0 ? 31.5 db insertion loss 50 mhz ? 2.2 ghz 2.2 ghz ? 4 ghz 4 ghz ? 6 ghz 6 ghz ? 7 ghz 1.3 1.7 2.4 2.5 1.6 2.0 2.8 2.9 db db db db attenuation error 0 db ? 15.5 db attenuation settings 50 mhz ? 2.2 ghz (0.15 + 1.5% of attenuation setting) - (0.1 + 2% of attenuation setting) db db >4 ghz ? 7 ghz + (0.25 + 6% of attenuation setting) - (0.25 + 0% of attenuation setting) db db 16 db ? 31.5 db attenuation settings 50 mhz ? 2.2 ghz + (0.2 + 1.5% of attenuation setting) - (0.1 + 2% of attenuation setting) db db >4 ghz ? 7 ghz + (0.3 + 7% of attenuation setting) - (0.25 + 2.5% of attenuation setting) db db return loss input port 50 mhz ? 4 ghz 4 ghz ? 7 ghz 20 17 db db return loss output port 50 mhz ? 4 ghz 4 ghz ? 7 ghz 17 15 db db relative phase 0 db ? 31.5 db attenuation settings 50 mhz ? 7 ghz 66 deg input 0.1db compression point 1 50 mhz ? 7 ghz 34 dbm input ip3 two tones at +18 dbm, 20 mhz spacing 6 ghz 65 dbm rf trise/tfall 10% / 90% rf 568 ns switching time 50% ctrl to 90% or 10% rf 1 s >2.2 ghz ? 4 ghz (0.15 + 3.5% of attenuation setting) - (0.1 + 1% of attenuation setting) db db >2.2 ghz ? 4 ghz (0.2 + 4% of attenuation setting) - (0.1 + 1% of attenuation setting) db db note 1: the input 0.1db compression point is a linearity figure of merit. refer to table 5 for the operating rf input power (50 ? )
document no. doc-47814-2 | ultracmos ? rfic solutions page 4 of 18 ?2013 peregrine semiconductor corp. all rights reserved. pe43705 product specification table 3. electrical specifications: 1 db steps @ +25c, v dd = 2.3v to 5.5v, (z s = z l = 50 ? ) unless otherwise noted parameter condition frequency min typ max unit operating frequency 50 8000 mhz attenuation range 1 db step 0 - 31 db insertion loss 50 mhz ? 2.2 ghz 2.2 ghz ? 4 ghz 4 ghz ? 6 ghz 6 ghz ? 8 ghz 1.3 1.7 2.4 2.8 1.6 2.0 2.8 3.2 db db db db attenuation error 0 db ? 15 db attenuation settings 50 mhz ? 2.2 ghz + (0.15 + 1.5% of attenuation setting) - (0.1 + 1% of attenuation setting) db db >2.2 ghz ? 4 ghz + (0.15 + 3.5% of attenuation setting) - (0.1 + 1% of attenuation setting) db db >4 ghz ? 8 ghz + (0.3 + 6.5% of attenuation setting) - (0.25 + 2% of attenuation setting) db db 16db ? 31 db attenuation settings 50 mhz ? 2.2 ghz + (0.2 + 1.5% of attenuation setting) - (0.1 + 1.5% of attenuation setting) db db >2.2 ghz ? 4 ghz + (0.2 + 4% of attenuation setting) - (0.1 + 1% of attenuation setting) db db >4 ghz ? 8 ghz + (0.3 + 7% of attenuation setting) - (0.3 + 4.5% of attenuation setting) db db return loss input port 50 mhz ? 4 ghz 4 ghz ? 8 ghz 20 15 db db return loss output port 50 mhz ? 4 ghz 4 ghz ? 8 ghz 17 13 db db relative phase 0 db ? 31 db attenuation settings 50 mhz ? 8 ghz 77 deg input 0.1db compression point 1 50 mhz ? 8 ghz 34 dbm input ip3 two tones at +18 dbm, 20 mhz spacing 6 ghz 65 dbm rf trise/tfall 10% / 90% rf 568 ns switching time 50% ctrl to 90% or 10% rf 1 s note 1: the input 0.1db compression point is a linearity figure of merit. refer to table 5 for the operating rf input power (50 ? )
pe43705 product specification ?2013 peregrine semiconductor corp. all rights reserved. document no. doc-47804-2 | www.psemi.com page 5 of 18 figure 3. pin configuration (top view) pin # pin name description 1 n/c no connect 2 v dd supply voltage 3 p /s serial/parallel mode select 4 a0 address bit a0 connection 5, 6, 8-17, 19, 20 gnd ground 7 rf1 1 rf1 port (rf input) 18 rf2 1 rf2 port (rf output) 21 a2 address bit a2 connection 22 a1 address bit a1 connection 23 le serial interface latch enable input 24 clk serial interface clock input 25 si serial interface data input 26 c16 (d6) 2 parallel control bit, 16 db 27 c8 (d5) 2 parallel control bit, 8 db 28 c4 (d4) 2 parallel control bit, 4 db 29 c2 (d3) 2 parallel control bit, 2 db 30 c1 (d2) 2 parallel control bit, 1 db 31 c0.5 (d1) 2 parallel control bit, 0.5 db 32 c0.25 (d0) 2 parallel control bit, 0.25 db pad gnd exposed pad: ground for proper operation table 4. pin descriptions notes: 1. rf pins 7 and 18 must be at 0v dc. the rf pins do not require dc blocking capacitors for proper operation if the 0v dc requirement is met 2. ground c0.25, c0.5, c1 c2, c4, c8, c16 if not in use table 5. operating ranges parameter symbol min typ max unit supply voltage v dd 2.3 5.5 v supply current i dd 130 200 a digital input high v ih 1.17 3.6 v digital input low v il -0.3 0.6 v digital input current i ctrl 15 a rf input power, cw p max,cw +28 dbm operating temperature range t op -40 +105 c rf input power, pulsed 1 p max,pulsed +31 dbm table 6. absolute maximum ratings parameter/condition symbol min max unit supply voltage v dd -0.3 5.5 v digital input voltage v ctrl -0.3 3.6 v maximum input power p max,abs +34 dbm storage temperature range t st -65 150 c esd voltage hbm 1 , all pins v esd,hbm 1500 v esd voltage mm 2 , all pins v esd,mm 200 v esd voltage cdm 3 , all pins v esd,cdm 250 v exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. notes: 1. human body model (mil-std 883 method 3015) 2. machine model (jedec jesd22-a115) 3. charged device model (jedec jesd22-c101) note 1: pulsed, 2.5% duty cycle of 4620 s period, 50 ?
document no. doc-47814-2 | ultracmos ? rfic solutions page 6 of 18 ?2013 peregrine semiconductor corp. all rights reserved. pe43705 product specification electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. switching frequency the pe43705 has a maximum 25 khz switching rate. switching frequency is defined to be the speed at which the dsa can be toggled across attenuation states. switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. moisture sensitivity level the moisture sensitivity level rating for the pe43705 in the 32-lead 5x5 mm qfn package is msl1. safe attenuation state transitions the pe43705 features a novel architecture to provide safe transition behavior when changing attenuation states. when rf input power is applied, positive output power spikes are prevented during attenuation state changes by optimized internal timing control. spurious performance the typical low-frequency spurious performance of the pe43705 is -140 dbm.
pe43705 product specification ?2013 peregrine semiconductor corp. all rights reserved. document no. doc-47804-2 | www.psemi.com page 7 of 18 table 8. serial attenuation word truth table parallel control setting attenuation setting rf1-rf2 d6 d5 d4 d3 d2 d1 d0 l l l l l l l reference i.l. l l l l l l h 0.25 db l l l l l h l 0.5 db l l l l h l l 1 db l l l h l l l 2 db l l h l l l l 4 db l h l l l l l 8 db h l l l l l l 16 db h h h h h h h 31.75 db table 7. parallel truth table attenuation word d7 d6 d5 d4 d3 d2 d1 d0 (lsb) l l l l l l l l reference i.l. l l l l l l l h 0.25 db l l l l l h l l 1 db l l l l h l l l 2 db l l l h l l l l 4 db l l h l l l l l 8 db l h l l l l l l 16 db l h h h h h h h 31.75 db attenuation setting rf1-rf2 l l l l l l h l 0.5 db address word address setting a7 (msb) a6 a5 a4 a3 a2 a1 a0 x x x x x l l l 000 x x x x x l l h 001 x x x x x l h l 010 x x x x x l h h 011 x x x x x h l l 100 x x x x x h l h 101 x x x x x h h l 110 x x x x x h h h 111 table 9. serial address word truth table table 10. serial addressable register map q15 q14 q13 q12 q11 q10 a7 a6 a5 a4 a3 a2 q9 q8 q7 q6 q5 q4 a1 a0 d7 d6 d5 d4 q3 q2 q1 q0 d3 d2 d1 d0 address word attenuation word lsb (first in) msb (last in) bits can either be set to logic high or logic low attenuation word is derived directly from the attenuation value. for example, to program the 18.25 db state at address 3: address word: xxxxx011 attenuation word: multiply by 4 and convert to binary 4 * 18.25 db 73 01001001 serial input: xxxxx01101001001 d7 must be set to logic low
document no. doc-47814-2 | ultracmos ? rfic solutions page 8 of 18 ?2013 peregrine semiconductor corp. all rights reserved. pe43705 product specification programming options parallel/serial selection either a parallel or serial addressable interface can be used to control the pe43705. the p /s bit provides this selection, with p /s = low selecting the parallel interface and p /s = high selecting the serial addressable interface. parallel mode interface the parallel interface c onsists of seven cmos- compatible control lines that select the desired attenuation state, as shown in table 7 . the parallel interface timing requirements are defined by figure 5 (parallel interface timing diagram), table 13 (parallel and direct interface ac characteristics) and switching time ( tables 1-3 ). for latched parallel programming, the latch enable (le) should be held low while changing attenuation state control values, then pulse le high to low ( per figure 5 ) to latch new attenuati on state into device. for direct parallel programming, the latch enable (le) line should be pulled high. changing attenuation state control values will change device state to new attenuation. direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). serial interface the serial addressable interf ace is a 16-bit serial-in, parallel-out shift register buffered by a transparent latch. the 16-bits make up two words comprised of 8- bits each. the first word is the attenuation word, which controls the state of the dsa. the second word is the address word, which is compared to the static (or programmed) logical states of the a0, a1 and a2 digital inputs. if there is an addr ess match, the dsa changes state; otherwise its current state will remain unchanged. figure 4 illustrates an example timing diagram for programming a state. it is required that all parallel control inputs be grounded when the dsa is used in serial addressable mode. the serial interface is co ntrolled using three cmos- compatible signals: serial -in (si), clock (clk), and latch enable (le). the si and clk inputs allow data to be serially entered into the shift register. serial data is clocked in lsb first, beginning with the attenuation word. the shift register must be loaded while le is held low to prevent the attenuat or value from changing as data is entered. t he le input should then be toggled high and brought low again, latching the new data into the dsa. attenuation word and address word truth tables are listed in table 8 and table 9 . a programming example of the serial register is illustrated in table 10. the serial timing diagram is illustrated in figure 4. power-up control settings the pe43705 will always initialize to the maximum attenuation setting (31.75 db) on power-up for both the serial addressable and latched parallel modes of operation and will remain in this setting until the user latches in the next programming word. in direct parallel mode, the dsa can be preset to any state within the 31.75 db range by pre-setting the parallel control pins prior to power-up. in this mode, there is a 400 s delay between the time the dsa is powered-up to the time the desired state is set. during this power-up delay , the device attenuates to the maximum attenuation setting (31.75 db) before defaulting to the us er defined state. if the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). dynamic operation between serial and parallel programming modes is possible. if the dsa powers up in serial mode ( p /s = high), all the parallel control inputs di[6:0] must be set to logic low. prior to toggling to parallel mode, the dsa must be programmed serially to ensure d[7] is set to logic low. if the dsa powers up in either latched or direct parallel mode, all parallel pins di[6:0] must be set to logic low prior to toggling to serial addressable mode ( p /s = high), and held low until the dsa has been programmed serially to ensure bit d[7] is set to logic low. the sequencing is only required once on power-up. once completed, the dsa may be toggled between serial and parallel programming modes at will.
pe43705 product specification ?2013 peregrine semiconductor corp. all rights reserved. document no. doc-47804-2 | www.psemi.com page 9 of 18 v dd = 3.4v or 5.0v, -40c < t a < 105c, unless otherwise specified v dd = 3.4v or 5.0v, -40c < t a < 105c, unless otherwise specified figure 4. serial timing diagram figure 5. latched parallel/direct parallel timing diagram parameter symbol min max unit serial clock frequency f clk 10 mhz serial clock high time t clkh 30 ns serial clock low time t clkl 30 ns last serial clock rising edge setup time to latch enable rising edge t lesu 10 ns latch enable min. pulse width t lepw 30 ns serial data setup time t sisu 10 ns serial data hold time t sih 10 ns parallel data setup time t disu 100 ns parallel data hold time t dih 100 ns address setup time t asu 100 ns address hold time t ah 100 ns parallel/serial setup time t pssu 100 ns parallel/serial hold time t psh 100 ns digital register delay (internal) t pd 10 ns parameter symbol min max unit latch enable minimum pulse width t lepw 30 ns parallel data setup time t disu 100 ns parallel data hold time t dih 100 ns parallel/serial setup time t pssu 100 ns parallel/serial hold time t psih 100 ns digital register delay (internal) t pd 10 ns digital register delay (internal, direct mode only) t dipd 5 ns valid t disu t dih di[6:0] le p/s t pssu t psh t lepw valid do[6:0] t dipd t pd table 13. parallel and direct interface ac characteristics table 12. serial interface ac characteristics d[7] must be set to logic low bits can either be set to logic high or logic low d[0] d[1] d[2] d[3] d[4] d[5] d[7] t sisu t clkl t lepw t sih t clkh si clk le p/s t lesu t pssu t psih valid t disu t pd t dih d[6] di[6:0] do[6:0] table 11. latch and clock specifications latch enable function 0 shift register clocked contents of shift register transferred to attenuator core shift clock x
document no. doc-47814-2 | ultracmos ? rfic solutions page 10 of 18 ?2013 peregrine semiconductor corp. all rights reserved. pe43705 product specification figure 6. 0.25 db step attenuation vs. frequency* typical performance data, 0.25 db step @ 25c and v dd = 3.3v unless otherwise specified figure 7. 0.25 db step, actual vs. frequency figure 8. 0.25 db major state bit error vs. attenuation setting figure 9. 0.25 db attenuation error vs. frequency * monotonicity is held so long as step- attenuation does not cross below ?0.25 db \ 0.25 \ 0.125 0 0.125 0.25 0 4 8 121620242832 step ? attenuation ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 0 5 10 15 20 25 30 35 0 4 8 12 16 20 24 28 32 actual ? attenuation ? (db) ideal ? attenuation ? (db) 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz \ 0.5 0 0.5 1 1.5 0 4 8 12 16 20 24 28 32 attenuation ? error ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz \ 0.5 0 0.5 1 1.5 0123456 attenuation ? error ? (db) frequency ? (ghz) 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db
pe43705 product specification ?2013 peregrine semiconductor corp. all rights reserved. document no. doc-47804-2 | www.psemi.com page 11 of 18 typical performance data, 0.5 db step @ 25c and v dd = 3.3v unless otherwise specified figure 10. 0.5 db step attenuation vs. frequency* figure 11. 0.5 db step, actual vs. frequency figure 12. 0.5 db major state bit error vs. attenuation setting figure 13. 0.5 db attenuation error vs. frequency * monotonicity is held so long as step- attenuation does not cross below ?0.5 db 0 5 10 15 20 25 30 35 0 4 8 12 16 20 24 28 32 actual ? attenuation ? (db) ideal ? attenuation ? (db) 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz \ 0.5 0 0.5 1 1.5 01234567 attenuation ? error ? (db) frequency ? (ghz) 0.5db 1db 2db 4db 8db 16db 31.5db \ 0.5 \ 0.25 0 0.25 0.5 0 4 8 121620242832 step ? attenuation ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz \ 0.5 0 0.5 1 1.5 0 4 8 121620242832 attenuation ? error ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz
document no. doc-47814-2 | ultracmos ? rfic solutions page 12 of 18 ?2013 peregrine semiconductor corp. all rights reserved. pe43705 product specification \ 1 \ 0.5 0 0.5 1 1.5 0 4 8 121620242832 attenuation ? error ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 8ghz \ 1 \ 0.5 0 0.5 1 1.5 012345678 attenuation ? error ? (db) frequency ? (ghz) 1db 2db 4db 8db 16db 31db \ 1 \ 0.5 0 0.5 1 0 4 8 12 16 20 24 28 32 step ? attenuation ? (db) attenuation ? setting ? (db) 0.2ghz 0.9ghz 1.8ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 8ghz typical performance data, 1 db step @ 25c and v dd = 3.3v unless otherwise specified figure 15. 1 db step, actual vs. frequency figure 14. 1 db step attenuation vs. frequency* figure 16. 1 db major state bit error vs. attenuation setting * monotonicity is held so long as step- attenuation does not cross below ?1.0 db 0 5 10 15 20 25 30 35 0 4 8 12 16 20 24 28 32 actual ? attenuation ? (db) ideal ? attenuation ? (db) 0.9ghz 2.2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 8ghz figure 17. 1 db attenuation error vs. frequency
pe43705 product specification ?2013 peregrine semiconductor corp. all rights reserved. document no. doc-47804-2 | www.psemi.com page 13 of 18 figure 18. insertion loss vs. temperature typical performance data, 1 db step @ 25c and v dd = 3.3v unless otherwise specified figure 19. input return loss vs. attenuation setting figure 20. output return loss vs. attenuation setting \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0123456789 return ? loss ? (db) frequency ? (ghz) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0123456789 return ? loss ? (db) frequency ? (ghz) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db figure 21. input return loss vs. temperature for 16 db attenuation setting figure 22. output return loss vs. temperature for 16 db attenuation setting \ 5 \ 4.5 \ 4 \ 3.5 \ 3 \ 2.5 \ 2 \ 1.5 \ 1 \ 0.5 0 0123456789 insertion ? loss ? (db) frequency ? (ghz) \ 40c 25c 85c 105c \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0123456789 return ? loss ? (db) frequency ? (ghz) \ 40c 25c 85c 105c \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0123456789 return ? loss ? (db) frequency ? (ghz) \ 40c 25c 85c 105c
document no. doc-47814-2 | ultracmos ? rfic solutions page 14 of 18 ?2013 peregrine semiconductor corp. all rights reserved. pe43705 product specification figure 23. relative phase error vs. attenuation setting figure 24. relative phase error for 31.75 db attenuation setting vs. frequency typical performance data @ 25c and v dd = 3.3v unless otherwise specified figure 25. attenuation error @ 900 mhz vs. temperature figure 26. attenuation error @ 1800 mhz vs. temperature figure 27. attenuation error @ 3000 mhz vs. temperature figure 28. iip3 vs. attenuation setting 0 20 40 60 80 100 012345678 relative ? phase ? error ? (deg) frequency ? (ghz) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db 0 10 20 30 40 50 60 70 \ 40 25 85 relative ? phase ? error ? (deg) temperature ? (deg ? c) 0.9ghz 1.8ghz 2ghz 3ghz 4ghz 5ghz 6ghz 60 62 64 66 68 70 72 74 2345678 input ? ip3 ? (dbm) ?? frequency ? (ghz) 0db 8db 16db \ 0.5 \ 0.25 0 0.25 0.5 0 4 8 12 16 20 24 28 32 attenuation ? error ? (db) attenuation ? setting ? (db) \ 40c 25c 85c 105c \ 0.5 \ 0.25 0 0.25 0.5 0.75 0 4 8 121620242832 attenuation ? error ? (db) attenuation ? setting ? (db) \ 40c 25c 85c 105c \ 0.5 \ 0.25 0 0.25 0.5 0.75 0 4 8 12 16 20 24 28 32 attenuation ? error ? (db) attenuation ? setting ? (db) \ 40c 25c 85c 105c
pe43705 product specification ?2013 peregrine semiconductor corp. all rights reserved. document no. doc-47804-2 | www.psemi.com page 15 of 18 evaluation kit the digital attenuator evaluation board (evb) was designed to ease customer evaluation of the pe43705 digital step attenuator. pe43705 evb supports direct parallel, latched parallel, and serial modes. evaluation kit setup connect the evb with the usb dongle board and usb cable as shown in figure 29 . direct parallel programming procedure direct parallel programming is suitable for manual operation without software programming. for manual direct parallel programming, position the parallel/serial ( p /s) select switch to the parallel (or left) position. the le pin of j1 (pin 15) must be tied to high voltage. switches d0?d6 are sp3t switches that enable the user to manually program the parallel bits. when d0?d6 are toggled to the high position, logic high is presented to the parallel input. when toggled to the low position, logic low is presented to the parallel input. setting d0?d6 to the auto position presents as open, which is set for software programming of latched parallel and serial mode. table 7 depicts the parallel programming truth table. latched parallel programming procedure for automated latched parallel programming, connect the usb dongle board and cable that is provided with the evaluation kit (evk) from the usb port of the pc to the j1 header of the pe43705 evb, and set the d0?d6 sp3t switches to the auto position. position the parallel/serial ( p /s) select switch to the parallel (or left) position. the evaluation software is written to operate the dsa in parallel mode. ensure that the software gui is set to latched parallel mode. use the software gui to enable the desired attenuation state. the software gui automatically programs the dsa each time an attenuation state is enabled. serial addressable programming procedure for automated serial programming, connect the usb dongle board and cable that is provided with the evaluation kit (evk) from the usb port of the pc to the j1 header of the pe43705 evb, and set the d0?d6 sp3t switches to the auto toggle position. position the parallel/serial ( p /s) select switch to the serial (or right) position. prior to programming, the user must define an address setting using the hdr4 header pin. jump the middle row of pins on the hdr4 header (a0?a2) to the lower row of pins to set logic low, or jump the middle row of pins to the upper row of pins to set logic high. if the hdr4 pins are left open, then 000 becomes the default address. the software gui is written to operate the dsa in serial mode. use the software gui to enable each setting to the desired attenuation state. the software gui automatically programs the dsa each time an attenuation state is enabled. figure 30. evaluation board layout prt-13505 figure 29. evaluation kit a0
document no. doc-47814-2 | ultracmos ? rfic solutions page 16 of 18 ?2013 peregrine semiconductor corp. all rights reserved. pe43705 product specification figure 31. evaluation board schematic doc-47827 notes: 1. use prt-13505 pcb 2. caution: contains parts and assemblies suscept ible to damage by electrostatic discharge (esd)
pe43705 product specification ?2013 peregrine semiconductor corp. all rights reserved. document no. doc-47804-2 | www.psemi.com page 17 of 18 top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features pin#1corner 5.00 5.00 3.300.05 3.300.05 3.50 3.50 0.50 0.240.05 (x32) 0.3750.05 (x32) 0.203 ref. 0.05 0.90 max 0.575 (x32) 0.290 (x32) 3.35 5.20 3.35 5.20 0.50 (x28) detail a 1 8 9 16 17 24 25 32 figure 32. package drawing 32-lead 5x5 qfn figure 33. top marking specification doc-01872 43705 yyww zzzzzz 17-0091 = pin 1 designator yyww = date code, last two digits of the year and work week zzzzzz = six digits of the lot number
document no. doc-47814-2 | ultracmos ? rfic solutions page 18 of 18 ?2013 peregrine semiconductor corp. all rights reserved. pe43705 product specification device orientation in tape top of device pin 1 tape feed direction table 14. ordering information figure 34. tape and reel drawing order code description package shipping method pe43705a-z pe43705 digital step attenuator 32-lead 5x5 mm qfn 3000 units / t&r ek43705-11 pe43705 evaluation ki t evaluation kit 1 / box notes: 1. 10 sprocket hole pitch cumulative tolerance .02 2. camber not to exceed 1 mm in 100 mm 3. material: ps + c 4. ao and bo measured as indicated 5. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier 6. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole ao = 5.25 mm bo = 5.25 mm ko = 1.1 mm advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregr ine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com .

▲Up To Search▲

Price & Availability of PE43705-14

	To Download PE43705-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .